The aforementioned commonly-owned, copending U.S. patent application Ser. No. 08/554,902 filed 9 Nov. 1995 and its corresponding PCT Patent Application No. PCT/US95/14844 filed 13 Nov. 95 (WO96/15458, published 23 May 1996), both by ELDRIDGE, GRUBE, KHANDROS and MATHIEU, disclose a probe card assembly. As illustrated, for example, in FIG. 5 therein, the probe card assembly (500) includes a probe card (502), a space transformer (506) having resilient contact structures (probe elements 524) mounted directly to and extending from terminals (522) on a surface thereof, and an interposer (504) disposed between the space transformer (506) and the probe card (502). The space transformer (506) and interposer (504) are “stacked up” so that the orientation of the space transformer (506), hence the orientation of the tips of the probe elements (524), can be adjusted without changing the orientation of the probe card. Suitable mechanisms (532, 536, 538, 546) for adjusting the orientation of the space transformer (506), and for determining what adjustments to make, are disclosed therein. Multiple die sites on a semiconductor wafer (508) are readily probed using the disclosed techniques, and the probe elements (524) can be arranged to optimize probing of an entire wafer (508). As shown, for example, in FIG. 2A therein, the resilient contact structures or probe elements (524) are suitably (but not limited to) composite interconnections elements (200) having a relatively soft core (206) overcoated by a relatively hard shell (218,220).
Generally, the present invention obviates the need for using a space transformer (e.g., 506) and an interposer (504) in a probe card assembly that may be adjusted in a manner similar to that described in the above-referenced patent applications.
Among the problems associated with using a space transformer component in a probe card assembly is that of matching the coefficients of thermal expansion of the space transformer to that of the wafer under test (WUT). Furthermore, in some instances, depending on the materials (e.g., ceramic layers, terminals, etc.) and processes employed in the manufacture of the space transformer component, it can be difficult to achieve a reliable mechanical connection between free-standing resilient (spring) contact elements mounted to the terminals of the space transformer under the stresses encountered when making repeated pressure connections to terminals of other electronic components, such as would be encountered when probing a sequence of WUTs or a series of die sites on a one or more WUTs.
The use of a separate interposer component in a probe card assembly can also be undesirable. Simply stated, it is one more component that must successfully be yielded and incorporated into the probe card assembly.
The present invention advantageously employs, but does not require applicant's own free-standing, resilient, “composite” interconnection elements, which are described in one or more of the above referenced commonly-owned patents and patent applications.
Commonly-owned U.S. patent application Ser. No. 08/152,812 filed 16 Nov. 1993 (now U.S. Pat. No. 4,576,211), and its counterpart commonly-owned copending “divisional” patent applications Ser. No. 08/457,479 filed Jun. 1, 1995 (status: pending) and Ser. No. 08/570,230 filed Dec. 11, 1995 (status: pending), all by KHANDROS, disclose methods for making resilient (spring) interconnection elements for microelectronics applications involving mounting an end of a flexible elongate core element (e.g., wire “stem” or “skeleton”) to a terminal on an electronic component coating the flexible core element and adjacent surface of the terminal with a “shell” of one or more materials having a predetermined combination of thickness, yield strength and elastic modulus to ensure predetermined force-to-deflection characteristics of the resulting spring contacts. Exemplary materials for the core element include gold. Exemplary materials for the coating include nickel and its alloys. The resulting spring contact element is suitably used to effect pressure, or demountable, connections between two or more electronic components, including semiconductor devices, and is well-suited to use as a probe element of a probe card assembly.
Commonly-owned, copending U.S. patent application Ser. No. 08/340,144 filed Nov 15, 1994 and its corresponding PCT Patent Application No. PCT/US94/13373 filed Nov. 16, 1994 (WO95/14314, published May 26, 1995), both by KHANDROS and MATHIEU, disclose a number of applications for the aforementioned spring contact elements, and also discloses techniques for fabricating contact pads at the ends of the spring contact elements. For example, in FIG. 14 thereof, a plurality of negative projections or holes, which may be in the form of inverted pyramids ending in apexes, are formed in the surface of a sacrificial layer (substrate). These holes are then filled with a contact structure comprising layers of material such as gold or rhodium and nickel. A flexible elongate element is mounted to the resulting contact structure and can be overcoated in the manner described hereinabove. In a final step, the sacrificial substrate is removed. The resulting spring contact has a contact pad having controlled geometry (e.g., sharp points) at its free end.
Commonly-owned, copending U.S. patent application Ser. No. 08/452,255 filed 26 May 95 and its corresponding PCT Patent Application No. PCT/US95/14909 filed 13 Nov. 95 (WO96/17278, published 6 Jun. 96), both by ELDRIDGE, GRUBE, KHANDROS and MATHIEU, disclose additional techniques and metallurgies for fabricating contact tip structures on sacrificial substrates, as well as techniques for transferring a plurality of spring contact elements mounted thereto, en masse, to terminals of an electronic component (see, e.g., FIGS. 11A–11F and 12A–12C therein). These patent applications also disclose techniques for fabricating free-standing “composite” resilient (spring) contact elements directly on silicon substrates, including on active devices.
Commonly-owned, copending U.S. Provisional Patent Application No. 60/005,189 filed 17 May 96 and its corresponding PCT Patent Application No. PCT/US96/08107 filed 24 May 96 (WO96/37332, published 28 Nov. 96), both by ELDRIDGE, KHANDROS, and MATHIEU, discloses techniques whereby a plurality of contact tip structures (see, e.g, #620 in FIG. 6B therein) are joined to a corresponding plurality of elongate contact elements (see, e.g., #632 of FIG. 6D therein) which are already mounted to an electronic component (#630). This patent application also discloses, for example in FIGS. 7A–7E therein, techniques for fabricating “elongate” contact tip structures in the form of cantilevers. The cantilever tip structures can be tapered, between one end thereof and an opposite end thereof. The cantilever tip structures of this patent application are suitable for mounting to already-existing (i.e., previously fabricated) raised interconnection elements (see, e.g., #730 in FIG. 7F) extending (e.g., free-standing) from corresponding terminals of an electronic component (see. e.g., #734 in FIG. 7F).
Commonly-owned, copending U.S. Provisional Patent Application No. 60/024,555 filed 26 Aug. 96, by ELDRIDGE, KHANDROS and MATHIEU, discloses, for example at FIGS. 2A–2C thereof, a technique whereby a plurality of elongate tip structures having different lengths than one another can be arranged so that their outer ends are disposed at a greater pitch than their inner ends. Their inner, “contact” ends may be collinear with one another, for effecting connections to electronic components having terminals disposed along a line, such as a centerline of the component.
The present invention addresses and is particularly well-suited to making interconnections to modern microelectronic devices having their terminals (bond pads) disposed at a fine-pitch. As used herein, the term “fine-pitch” refers to microelectronic devices that have their terminals disposed at a spacing of less than 5 mils, such as 2.5 mils or 65 μm.
Individual semiconductor (integrated circuit) devices (dies) are typically produced by creating several identical devices on a semiconductor wafer, using know techniques of photolithography, deposition, and the like. Generally, these processes are intended to create a plurality of fully-functional integrated circuit devices, prior to singulating (severing) the individual dies from the semiconductor wafer. In practice, however, certain physical defects in the wafer itself and certain defects in the processing of the wafer inevitably lead to some of the dies being “good” (fully-functional) and some of the dies being “bad” (non-functional).
It is generally desirable to be able to identify which of the plurality of dies on a wafer are good dies prior to their packaging, and preferably prior to their being singulated from the wafer. To this end, a wafer “tester” or “prober” may advantageously be employed to make a plurality of discrete pressure connections to a like plurality of discrete connection pads (bond pads) on the dies. In this manner, the semiconductor dies can be tested and exercised, prior to singulating the dies from the wafer.
A conventional component of a wafer tester is a “probe card” to which a plurality of probe elements are connected tips of the probe elements effecting the pressure connections to the respective bond pads of the semiconductor dies.
Certain difficulties are inherent in any technique for probing semiconductor dies. For example, modern integrated circuits include many thousands of transistor elements requiring many hundreds of bond pads disposed in close proximity to one another (e.g., 5 mils center-to-center). Moreover, the layout of the bond pads need not be limited to single rows of bond pads disposed close to the peripheral edges of the die (See, e.g., U.S. Pat. No. 5,453,583).
To effect reliable pressure connections between the probe elements and the semiconductor die one must be concerned with several parameters including, but not limited to: alignment, probe force, overdrive, contact force, balanced contact force, scrub, contact resistance, and planarization. A general discussion of these parameters may be found in U.S. Pat. No. 4,837,622, entitled HIGH DENSITY PROBE CARD, incorporated by reference herein, which discloses a high density epoxy ring probe card including a unitary printed circuit board having a central opening adapted to receive a preformed epoxy ring array of probe elements.
Generally, prior art probe card assemblies include a plurality of tungsten needles extending as cantilevers from a surface of a probe card. The tungsten needles may be mounted in any suitable manner to the probe card, such as by the intermediary of an epoxy ring, as discussed hereinabove. Generally, in any case, the needles are wired to terminals of the probe card through the intermediary of a separate and distinct wire connecting the needles to the terminals of the probe card.
Probe cards are typically formed as circular rings, with hundreds of probe elements (needles) extending from an inner periphery of the ring (and wired to terminals of the probe card). Circuit modules, and conductive traces (lines) of preferably equal length, are associated with each of the probe elements. This ring-shape layout makes it difficult, and in some cases impossible, to probe a plurality of unsingulated semiconductor dies (multiple sites) on a wafer, especially when the bond pads of each semiconductor die are arranged in other than two linear arrays along two opposite edges of the semiconductor die.
Wafer testers may alternately employ a probe membrane having a central contact bump area, as is discussed in U.S. Pat. No. 5,422,574, entitled LARGE SCALE PROTRUSION MEMBRANE FOR SEMICONDUCTOR DEVICES UNDER TEST WITH VERY HIGH PIN COUNTS, incorporated by reference herein. As noted in this patent, “A test system typically comprises a test controller for executing and controlling a series of test programs, a wafer dispensing system for mechanically handling and positioning wafers in preparation for testing and a probe card for maintaining an accurate mechanical contact with the device-under-test (DUT).” (column 1, lines 41–46).
Additional references, incorporated by reference herein, as indicative of the state of the art in testing semiconductor devices, include U.S. Pat. No. 5,442,282 (TESTING AND EXERCISING INDIVIDUAL UNSINGULATED DIES ON A WAFER); U.S. Pat. No. 5,382,898 (HIGH DENSITY PROBE CARD FOR TESTING ELECTRICAL CIRCUITS); U.S. Pat. No. 5,378,982 TEST PROBE FOR PANEL HAVING AN OVERLYING PROTECTIVE MEMBER ADJACENT PANEL CONTACTS); U.S. Pat. No. 5,339,027 (RIGID-FLEX CIRCUITS WITH RAISED FEATURES AS IC TEST PROBES); U.S. Pat. No. 5,180,977 (MEMBRANE PROBE CONTACT BUMP COMPLIANCY SYSTEM); U.S. Pat. No. 5,066,907 (PROBE SYSTEM FOR DEVICE AND CIRCUIT TESTING); U.S. Pat. No. 4,757,256 (HIGH DENSITY PROBE CARD); U.S. Pat. No. 4,161,692 (PROBE DEVICE FOR INTEGRATED CIRCUIT WAFERS); and U.S. Pat. No. 3,990,689 (ADJUSTABLE HOLDER ASSEMBLY FOR POSITIONING A VACUUM CHUCK).
Generally, interconnections between electronic components can be classified into the two broad categories of “relatively permanent” and “readily demountable”.
An example of a “relatively permanent” connection is a solder joint. Once two components are soldered to one another, a process of unsoldering must be used to separate the components. A wire bond is another example of a “relatively permanent” connection.
An example of a “readily demountable” connection is rigid pins of one electronic component being received by resilient socket elements of another electronic component. The socket elements exert a contact force (pressure) on the pins in an amount sufficient to ensure a reliable electrical connection therebetween.
Interconnection elements intended to make pressure contact with terminals of an electronic component are referred to herein as “springs” or “spring elements”. Generally, a certain minimum contact force is desired to effect reliable pressure contact to electronic components (e.g., to terminals on electronic components). For example, a contact (load) force of approximately 15 grams (including as little as 2 grams or less and as much as 150 grams or more, per contact) may be desired to ensure that a reliable electrical connection is made to a terminal of an electronic component which may be contaminated with films on its surface, or which has corrosion or oxidation products on its surface. The minimum contact force required of each spring demands either that the yield strength of the spring material or that the size of the spring element are increased. As a general proposition, the higher the yield strength of a material, the more difficult it will be to work with (e.g., punch, bend, etc.). And the desire to make springs smaller essentially rules out making them larger in cross-section.
Probe elements are a class of spring elements of particular relevance to the present invention. Prior art probe elements are commonly fabricated from tungsten, a relatively hard (high yield strength) material. When it is desired to mount such relatively hard materials to terminals of an electronic component, relatively “hostile” (e.g., high temperature) processes such as brazing are required. Such “hostile” processes are generally not desirable (and often not feasible) in the context of certain relatively “fragile” electronic components such as semiconductor devices. In contrast thereto, wire bonding is an example of a relatively “friendly” processes which is much less potentially damaging to fragile electronic components than brazing. Soldering is another example of a relatively “friendly” process. However, both solder and gold are relatively soft (low yield strength) materials which will not function well as spring elements.
A subtle problem associated with interconnection elements, including spring contact elements, is that, often, the terminals of an electronic component are not perfectly coplanar. Interconnection elements lacking in some mechanism incorporated therewith for accommodating these “tolerances” (gross non-planarities) will be hard pressed to make consistent contact pressure contact with the terminals of the electronic component.
The following U.S. patents, incorporated by reference herein, are cited as being of general interest vis-a-vis making connections, particularly pressure connections, to electronic components: U.S. Pat. No. 5,386,344 (FLEX CIRCUIT CARD ELASTOMERIC CABLE CONNECTOR ASSEMBLY); U.S. Pat. No. 5,336,380 (SPRING BIASED TAPERED CONTACT ELEMENTS FOR ELECTRICAL CONNECTORS AND INTEGRATED CIRCUIT PACKAGES); U.S. Pat. No. 5,317,479 (PLATED COMPLIANT LEAD); U.S. Pat. No. 5,086,337 (CONNECTING STRUCTURE OF ELECTRONIC PART AND ELECTRONIC DEVICE USING THE STRUCTURE); U.S. Pat. No. 5,067,007 (SEMICONDUCTOR DEVICE HAVING LEADS FOR MOUNTING TO A SURFACE OF A PRINTED CIRCUIT BOARD); U.S. Pat. No. 4,989,069 (SEMICONDUCTOR PACKAGE HAVING LEADS THAT BREAK-AWAY FROM SUPPORTS); U.S. Pat. No. 4,893,172 (CONNECTING STRUCTURE FOR ELECTRONIC PART AND METHOD OF MANUFACTURING THE SAME); U.S. Pat. No. 4,793,814 (ELECTRICAL CIRCUIT BOARD INTERCONNECT); U.S. Pat. No. 4,777,564 (LEADFORM FOR USE WITH SURFACE MOUNTED COMPONENTS); U.S. Pat. No. 4,764,848 (SURFACE MOUNTED ARRAY STRAIN RELIEF DEVICE); U.S. Pat. No. 4,667,219 (SEMICONDUCTOR CHIP INTERFACE); U.S. Pat. No. 4,642,889 (COMPLIANT INTERCONNECTION AND METHOD THEREFOR); U.S. Pat. No. 4,330,165 (PRESS-CONTACT TYPE INTERCONNECTORS); U.S. Pat. No. 4,295,700 (INTERCONNECTORS); U.S. Pat. No. 4,067,104 (METHOD OF FABRICATING AN ARRAY OF FLEXIBLE METALLIC INTERCONNECTS FOR COUPLING MICROELECTRONICS COMPONENTS); U.S. Pat. No. 3,795,037 (ELECTRICAL CONNECTOR DEVICES); U.S. Pat. No. 3,616,532 (MULTILAYER PRINTED CIRCUIT ELECTRICAL INTERCONNECTION DEVICE); and U.S. Pat. No. 3,509,270 (INTERCONNECTION FOR PRINTED CIRCUITS AND METHOD OF MAKING SAME).